1. Field of the Disclosure
The disclosure relates to a method for forming a bit line of a semiconductor device and, more particularly, to a method for forming a bit line of a semiconductor device, in which tungsten is deposited just after depositing a metallic barrier layer, a nitride layer is deposited after forming a bit line to prevent the bit line from oxidation due to the exposure of tungsten, and then a rapid thermal treatment is performed, whereby the contact resistance of the bit line is stabilized, and an additional process of depositing TiN due to the micro crack generated by the rapid thermal treatment is not needed, so the manufacturing process becomes simple and the productivity of manufacturing the semiconductor device is improved.
2. Description of Related Art
The degree of integration and processing speed of semiconductor memory devices, especially dynamic random access memory (DRAM), have steadily increased. In order to make high speed devices, it is necessary to secure a stable contact resistance and to reduce the sheet resistance of a bit line and a word line. Therefore, there is a need to use a material of low resistance in forming a line. For example, in forming a word line of a DRAM, polysilicon has been used for 4 megabytes DRAM, and tungsten silicide was used for 16 megabytes DRAM. There have been continuous attempts to use titanium silicide having a resistance lower than such a material in manufacturing a DRAM of greater integrity than one gigabyte, and even a pure metal such as tungsten having an even lower resistance than silicide has been seriously considered.
As is well-known, the sub-layer formed with a bit line contact is composed of an impurity diffusion area (N− type or P+ type impurity area) of a peripheral circuit area, a tungsten silicide layer of a gate electrode, or a polysilicon pad of an active area. A barrier material is required to lower the contact resistance between the different areas and prevent the current leakage, and a titanium/titanium nitride layer construction has generally been used as the barrier material. Also, tungsten is used as the bit line material. Here, titanium reacts with silicon exposed at the lower area during the subsequent thermal treatment to form titanium silicide (TiSix), which improves the contact resistance, and the titanium nitride layer functions as a protecting layer for preventing the instability of interface by protecting the permeation of fluorine gas generated by the subsequent deposition process of tungsten, to the lower layer material.
Hereinafter, a conventional method for forming a bit line of a semiconductor is illustrated with reference to the accompanying drawings.
FIG 1A through FIG. 1G are cross-sectional views for illustrating consecutive steps of a conventional method for forming a bit line of a semiconductor device.
As shown in FIG. 1A, a first insulation layer 12 is formed on a semiconductor substrate 11, and a hole is formed to expose the substrate by removing a part of the first insulation layer 12. A plug 13 is then formed by filling up the hole with polysilicon, a second insulation layer 14 is formed on the first insulation layer 12 including the plug 13, and the upper side of the second insulation layer 14 is planarized.
As shown in FIG. 1B, a trench is formed to form a bit line by etching the second insulation layer 14 so that the plug 13 is exposed.
At this time, the width of line is about 0.20 μm to 0.25 μm of CD (critical dimension) in the case of using a DUV (Deep Ultraviolet) stepper.
Here, to make the line narrower, a third insulation layer 15 forming a sidewall on the overall surface including the trench is thinly formed.
In that situation, the third insulation layer 15 is formed by lower pressure deposition providing superior step coverage.
As shown in FIG. 1C, a photoresist 16 is spread on the front surface of the third insulation layer 15, and then the photoresist 16 is patterned.
As shown in FIG. 1D, an etching process is performed by using the patterned photoresist 16 as a mask, to form a contact hole 17b exposing the bit line contact 17a and the semiconductor substrate 11.
The etching at this time is dry etching.
FIG. 1E shows a region designated ‘A’ in FIG. 1D in detail. After the bit line contact 17a is formed, a cleaning process is performed to remove a natural oxide layer in the bit line contact 17a. 
Also, a barrier layer 18 composed of a titanium (Ti) layer and a titanium nitride (TiN) layer is formed on a front surface including the contact 17a, in order to reduce the contact resistance of the bit line.
After that, a titanium silicide (TiSi2) layer 19 is formed on the barrier layer 18 by thermal treatment at high temperature, in order to minimize the contact resistance with respect to the substrate 11.
In such a situation, the titanium silicide layer 19 is formed so as not to come into contact with an overhang area in the bit line contact 17a. 
As shown in FIG. 1F, a tungsten layer 20 is formed on the front surface including the titanium silicide layer 19.
Next, as shown in FIG. 1G, a bit line including of the barrier layer 18, the titanium silicide layer 19, and the tungsten layer 20 is formed by a CMP (chemical-mechanical planarization) process.
However, in such a conventional method, to prevent the cohesion of TiSi2 during the rapid thermal treatment at the temperature of 800° C. to 850° C., the titanium (Ti) layer and the titanium nitride (TiN) layer are deposited consecutively before the thermal treatment, and in such a situation, a micro crack is generated on the titanium nitride (TiN) layer by rapid thermal stress, and a defect may occur due to the fluorine gas used while tungsten (W) is being deposited.